In a data transmission system, the quality of transmitting and receiving data will be affected by an impedance matching, particularly for the increasingly faster speed of data transmissions.
Referring to FIG. 1 for a schematic circuit diagram of performing an impedance matching in accordance with a prior art, an external resistor is used for impedance matching, and the conventional method is simple, easy and direct, but it still has the following drawbacks:    (1) The conventional method requires external cascade resistors and incurs a higher system cost.    (2) Since the impedance seen by the reflection waves is the sum of the internal output driver impedance and the impedance of external cascade resistors, and the internal output driver impedance varies with an environment factor of a chip such as at least one of manufacture process, operational voltage, and temperature (P.V.T.), the conventional method cannot be used to achieve a better impedance matching.
Referring to FIG. 2 for a schematic circuit diagram of performing impedance matching by a self-calibrated resistor matrix in a chip in accordance with a prior art, the resistor matrix is adopted in the chip, and the self-calibration mechanism is adopted for the impedance matching. This conventional method integrates the resistor matrix into the chip to lower the system cost, wherein the resistor matrix is comprised of a plurality of resistors and a plurality of switches, but its drawback resides on that the resistor matrix used in the chip occupies a larger area and incurs a higher die cost.